November 20-21, 2001

Control of Ion Energy Distribution at Substrates During Plasma Etching

Amy E. Wendt, and S. B. Wang (Univ. of Wisconsin-Madison)

1

High-Efficiency Neutral-Beam Generation using Inductively Coupled Plasma

Keisuke Sakamoto, Katsunori Ichiki*, and Seiji Samukawa (Institute of Fluid Science, Tohoku Univ., *Ebara Research Co., Ltd.)

11

Study of sub-30 nm Gate Etching Technology

Masatoshi Nagase, N. Ikezawa, K. Tokashiki, M. Takimoto, and K. Kasama (ULSI Device Development Div., NEC Corp.)

17

Surface Reaction Control for 240-nm Pitch Metal Etching

Naoyuki Kofuji, Takashi Tatsumi*, Eiji Matsumoto*, Kotaro Fujimoto**, Naoshi Itabashi, Masaru Izawa, Takashi Fujii*, and Shinichi Tachi (Central Research Lab. Hitachi, Ltd., *Kasado Semiconductor Equipment Product Div., Hitachi, Ltd., **Hitachi Techno Eng. Co., Ltd.)

23

Etching Reactions of Fluorine on Si Surfaces using Molecular Dynamics Simulations

Tracy A. Schoolcraft (Dept. of Chemistry, Shippensburg Univ.)

29

High-Rate and High-Selective Ruthenium Etching using Ozone Gas

Sukeyoshi Tsunekawa, M. Nakahara*, T. Arai**, K. Watanabe***, T. Yunogami****, and K. Kuroki***** (Heating & Lighting Div., Hitachi, Ltd., *Production Eng. Research Lab., Hitachi, Ltd., **Semiconductor & Integrated Circuits Div., Hitachi, Ltd., On leave from Hitachi Instruments Service Co., Ltd., ****Semiconductor Leading Edge Technologies, Inc., *****ELPIDA Memory, Inc.)

37

Reduction of Vacuum-Ultraviolet Radiation Damage in Pulse-Time-Modulated Plasma

Yasushi Ishikawa, Mitsuru Okigawa*, Shinya Kumagai, and Seiji Samukawa (Institute of Fluid Science, Tohoku Univ., *Semiconductor Company System LSI Div. CCD Development, Sanyo Electric Co., Ltd.)

43

Dry Processing of High Aspect Ratio Si Microstructures for MEMS

Stella W. Pang (The Univ. of Michigan)

49

High Rate Deep Si Etching

Itsuko Sakai, Keiichi Sasaki, Kazuhiro Tomioka, Tokuhisa Ohiwa, Makoto Sekine, Takanori Mimura*, and Kazuya Nagaseki* (Process & Manufacturing Eng. Center, Toshiba Corp. Semiconductor Company, *ES Development Dept., Tokyo Electron AT Ltd.)

57

Control of Etching Residue in Deep Trench Etching of Borosilicate Glass for MEMS Fabrication

Takanori Ichiki, Yoshinari Sugiyama, and Yasuhiko Horiike* (Dept. of Electric and Electronics Eng., Toyo Univ., *Dept. of Materials Science, School of Eng., The Univ. of Tokyo)

63

Observation of Fluorocarbon Beam Interaction with Si and SiO2 Surfaces

Hirotaka Toyoda, Yasuaki Hori, Hisayuki Morishima, and Hideo Sugai (Dept. of Electrical Eng., Nagoya Univ.)

69

Detection of Negative Ions by Developing Their Flux Profile on the Surface of a Biased Target

E. Stamate*,**, K. Ohe*, and H. Sugai** (*Dept. of Systems Eng., Nagoya Institute of Technology, **Dept. of Electrical Eng., Nagoya Univ.)

75

Correlation between the Property of Fluorocarbon Film and the Surface Production of CFx

Koichi Sasaki, Tsuyoshi Iida, Noriharu Takada, and Kiyoshi Kadota (Dept. of Electronics, Nagoya Univ.)

81

Electron Temperature Control by Rare Gas Mixing with Metastable Atom Contribution

Tatsuo Ishijima, Masami Ikeda, and Hideo Sugai (Dept. of Electrical Eng., Nagoya Univ.)

87

The Nature and Benefits of Plasma Confinement

Takehito Koshizawa, Peter Loewenhardt, Mukund Srinivasan, and James Tietz (Lam Research Corp.)

93

Numerical Analysis of Electromagnetic Field in Surface Wave Plasma Device with Cup-Type Dielectrics

Shinichi Kitamura, Minoru Nomura, and Sumio Kogoshi (Dept. of Electrical Eng., Faculty of Science and Technology, Science Univ. of Tokyo)

99

High Rate, High Aspect Ratio Deep Silicon Etch Technology for Trench Capacitor, Trench Isolation, MEMS & MOEMS Applications

Padmapani Nallan, A. H. Khan, Ajay Kumar, and Dragan Podlesnik (Applied Materials, Inc.)

105

Si Deep Trench Etching with Aspect Ratio Exceeding Fifty

Satoshi Shimonishi, Takanori Matsumoto*, Shuichi Taniguchi, Keiichi Takenaka, Itsuko Sakai, Tokuhisa Ohiwa, Fumihiko Higuchi**, and Katsumi Horiguchi** (Process & Manufacturing Eng. Center, Toshiba Corp. Semiconductor Company, *Advanced Memory Product Development Dept., Memory Div., Toshiba Corp. Semiconductor Company, **ES Process Development Dept., Tokyo Electron AT Ltd.)

111

< DPS2001 Young Researcher Award Winner >

Effects of O2 Plasma Cleaning and Subsequent H2 Addition to C4F8 in Deep Si Etching Process

Takeshi Kuriyagawa, Youjiro Tezuka, Takayuki Fukasawa, Yuzuru Takamura, and Yasuhiro Horiike (Dept. of Materials Science, The Univ. of Tokyo)

117

Impact of Chamber History on Process Stability in the Gate Etching Employing Cl2- and HBr-based ECR Plasmas

Suguru Tabara (Process Technology Dept. 2, Technology Div., ROHM HAMAMATSU Co., Ltd.)

123

Atomic-scale Surface Analysis of Silicon Etching by Cl/O Plasmas

Hiroaki Ohta and Satoshi Hamaguchi (Dept. of Fundamental Energy Science, Kyoto Univ.)

129

The Effect of Neutral Transport on Silicon Redeposition During Etch

Mark W. Kiehlbauch*,** and David B. Graves* (*Dept. of Chemical Eng., Univ. of California, **Conductor Etch, Lam Research Corp.)

135

Study of Plasma-Surface Interactions on SiO2 and Organic Low-k Dielectric by using Plasma-Beam Irradiation

Kazuaki Kurihara, Y. Yamaoka, K. Karahashi, M. Sekine, and M. Nakamura (Environmental Etching Technology Lab., ASET)

141

Etching of Organic Low-k Film in ICP and UHF Plasma Employing N2/H2 and N2/NH3 Gases

Hisao Nagai, Yoritsugu Maeda, Mineo Hiramatsu*, Masaru Hori, and Toshio Goto (Dept. of Quantum Eng., Nagoya Univ., *Dept. of Electrical and Electronic Eng., Meijo Univ.)

147

Etching Characteristics of SiOC Film for Low-k Dielectrics

Takeshi Yamashita, Shingo Tomohisa*, Shigenori Sakamori**, Michinari Yamanaka, Nobuo Fujiwara**, Tomoyuki Sasaki, and Hiroshi Miyatake** (ULSI Process Technology Development Center, Matsushita Electric Industrial Co., Ltd., *Advanced Technology R&D Center, Mitsubishi Electric Corp., **ULSI Development Center, Mitsubishi Electric Corp.)

153

Application of MSQ (k = 2.5) to Al Multi-layer Wiring

Toyokazu Sakata, Naokatsu Ikegami, Motoki Kobayashi, and Jun Kanamori (Advanced VLSI Research Center, Oki Electric Industry Co., Ltd.)

159

Mechanism of Cu Oxidation in Ashing Process

Akihiro Kojima, Takayuki Sakai, and Tokuhisa Ohiwa (Process & Manufacturing Eng. Center, Toshiba Corp. Semiconductor Company)

165

Deposition of Pure Copper Thin Films by H-assisted Plasma CVD using a New Cu Complex Cu(EDMDD)2

Kosuke Takenaka, Hong Jie Jin, Masao Onishi, Kazunori Koga, Masaharu Shiratani, Yukio Watanabe, and Tsuyoshi Watanabe* (Graduate School of Information Science and Electrical Eng., Kyushu Univ., *Asahi Denka Kogyo K.K.)

169

Characterization of Hafnium Silicate Films Fabricated by Plasma-Enhanced Chemical Vapor Deposition

Hiromitsu Kato, Tomohiro Nango, Takeshi Miyagawa, Takahiro Katagiri, Yoshimichi Ohki, Kwang Soo Seol*, and Makoto Takiyama** (Waseda Univ., *RIKEN, **Wacker NSCE Corp.)

175

< DPS2001 Young Researcher Award Winner >

Structure and Pore Formation of Fluorocarbon Films Polymerized in Plasmas

Kazuo Takahashi, Atsushi Itoh*, Kunihide Tachibana*, Kouichi Ono, and Yuichi Setsuhara (Dept. of Aeronautics and Astronautics, Kyoto Univ., *Dept. of Electronic Science and Eng., Kyoto Univ.)

181

< DPS2001 Best Paper Award Winner >

A New Stacked Mask Process (S-MAP) Utilizing Spun-on Carbon Film for Sub-130 nm Etching

Junko Abe, Hisataka Hayashi, Daizo Kishigami, Yasuhiko Sato, Eishi Shiobara, Tsuyoshi Shibata, Yasunobu Onishi, and Tokuhisa Ohiwa (Process & Manufacturing Eng. Center, Toshiba Corp. Semiconductor Company)

187

Flash Step : A Solution for Open Pad Residue Removal in Dielectric Etch

Judy Wang, Jingbao Liu, Jamie Hsu, Neung-ho Shin, Claes Bjorkman, Hongching Shan, and Bryan Pu (Applied Materials Inc.)

193

Highly Selective SAC Process Trends in Dual Frequency Confined Plasma Etch Systems

T. Chien, H. Y. Kim, J. P. Lee, W. S. Lee*, J. Kim*, J. W. Shon, and D. Keil (Lam Research Corp., *Samsung R&D Center, Samsung Electronics Co., Ltd.)

197

Polymer Deposition Control in Dielectric Etch; Integration of an in-situ Dry Cleaning (DC) Source for an MERIE Chamber

Mahmoud Dahimene, Hongching Shan, Kenny Doan, and Joshua Tsui (Dielectric Etch Div., Applied Materials)

201

Effects of CH2F2 on Selectivity and Contact Profile in C4F6/O2/Ar Plasma During

High Aspect Ratio Contact Etch Process Hyun-Kyu Ryu, Chang-Heon Park, Yun-Seok Cho, Jin-Woong Kim, and Hee-Koo Yoon (Memory R&D Div., Hynix Semiconductor Inc.)

207

Control of Wall Polymer Deposition and Stabilization of Radical Density in Fluorocarbon Inductively-Coupled Plasmas

Keiji Nakamura and Noriaki Kasuya (Dept. of Electrical Eng., Chubu Univ.)

213

Self-Aligned Contact Etching for Sub-0.15 μm

Yu-Chi Sun and Tze-Yao Huang (Module Development II-Advanced Etch Module, NANYA Technology Corp.)

219

Mechanism of Large Nitride Step Formation in 0.12 μm SAC Process

J. W. Shon, T. Chien, H. Y. Kim, W. S. Lee*, J. Kim*, D. Keil (Lam Research Corp., *Samsung R&D Center, Samsung Electronics Co., Ltd.)

225

Developments of Environmentally benign Silicon Oxide Etching Process and Novel Zero-emission PFC Abatement System

Kazushi Fujita, Mikio Nagai, Akira Suzuki, Masafumi Ito*, Masaru Hori, and Toshio Goto (Dept. of Quantum Eng., Graduate School of Eng., Nagoya Univ., *Dept. of Opto-Mechatronics, Faculty of Systems Eng., Wakayama Univ.)

229

Removal of Residues During Photoresist Ashing of Low k Dual Damascene Structures

Tom Kropewnicki, Mahmoud Dahimene, Jerry Pender, Huong Nguyen, Henry Fong, Raymond Hung, and Claes Bj?rkman (Dielectric Etch Div., Applied Materials, Inc.)

235

A Novel Approach to Reduce Via Corner Faceting in the Via-First, No Middle Stop Layer Dual Damascene Trench Etch

Yun-Sang Kim, Kenny L Doan, Claes Bj?kman, Alex Paterson, Zhifeng Sui, and Hongching Shan (Applied Materials, Inc.)

241

N2 Addition Effect on Highly Accurate Organic Low-k Etching Process

Yasuhiro Morikawa, Masanori Ozawa, Wei Chen, Toshio Hayashi, and Taijiro Uchida (Institute for Semiconductor Technologies, ULVAC, Inc.)

247

Sub 0.12 μm Nitride Hard Mask Open Process with ArF Photoresist

Jisoo Kim, Y. S. Chae, W. S. Lee, J. W. Shon, D. S. Nam, H. W. Kim, Y. Kang, C. J. Kang, and J. T. Moon (Semiconductor R&D Center, Samsung Electronics Co., Ltd.)

253

Effects of Inert Gas Additives on the Etching of Silver using Inductively Coupled Cl2-based Plasmas

Y. J. Lee, S. D. Park, B. K. Song, M. P. Hong*, and G. Y. Yeom (Dept. of Materials Eng., Sungkyunkwan Univ., *AMLCD Div., Samsung Electronics Co., Ltd.)

259

Effect of N-base Additive Gases to C4F8O/O2 on the Global Warming Effect in the Silicon Nitride PECVD Plasma Cleaning

J. H. Kim, J. W. Bae, C. H. Oh, K. J. Kim, N. E. Lee, and G. Y. Yeom, (Dept. of Materials Eng., Sungkyunkwan Univ.)

265

Diagnostics of RF and Microwave Discharges by Laser Spectroscopic Electric Field Measurements

Uwe Czarnetzki, V. A. Kadetov, D. Luggenh?scher, and H. F. D?bele (Institut f?r Experimentelle Physik, Univ. Essen)

271

Silicon Oxide Selective Etching Processes in UHF Plasma Employing Low Global Warming Potential Gases

Yoritsugu Maeda, Hisao Nagai, Toshiyuki Tanaka, Masaru Hori, and Toshio Goto (Dept. of Quantum Eng., Graduate School of Eng., Nagoya Univ.)

279

Control of Selectivity and Profile by Wafer Temperature in Highly Selective Contact Hole Etching

Kazumasa Yonekura, Hiroshi Matsuo, Nobuo Fujiwara, and Hiroshi Miyatake (ULSI Development Center, Mitsubishi Electric Corp.)

285

Profile and Equipment Simulation for the Self-Aligned Contact Etch Process with C4F8 Plasmas

Won-Young Chung, Tai-Kyung Kim, Jae-Joon Oh*, Kang-Ill Seo**, Young-Kwan Park, and Jeong-Taek Kong (CAE Team, Semiconductor R&D Center, Samsung Electronics Co., Ltd., *CSE Center, Samsung Advanced Institute of Technology, **Process Technology Team, Semiconductor R&D Center, Samsung Electronics Co., Ltd.)

291

Interferometric Etch to Depth Control for Dielectric Etch Applications

Zhifeng Sui, Coriolan Frum, and Hongching Shan (Applied Materials, Inc.)

297

Dangling Bond Observation During Fluorocarbon Plasma Etching Processes using In-Vacuo Electron-Spin-Resonance Technique

Kenji Ishikawa, Mitsuru Okigawa, Makoto Sekine, Moritaka Nakamura, Tetsuji Yasuda*, Junichi Isoya*, and Satoshi Yamasaki* (Association of Super-advanced Electronics Technology (ASET), *Joint Research Center of Atom Technology (JRCAT))

301